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Logic gate
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51	CyberWorkBench® High-Level Synthesis and Verification by: SystemC High-Level Synthesis and Verification Add to Reading List Source URL: www.aldec.com Language: English - Date: 2013-08-07 16:44:00 Fabless semiconductor companies Hardware description languages Logic design Aldec Field-programmable gate array Xilinx High-level synthesis Altera SystemC Electronic engineering Digital electronics Electronic design automation
52	1 Yosys Application Note 010: Converting Verilog to BLIF Clifford Wolf November 2013 Add to Reading List Source URL: www.clifford.at Language: English - Date: 2015-02-09 07:25:25 Digital electronics Logic design Verilog Logic synthesis Field-programmable gate array High-level synthesis Finite-state machine VHDL AS/400 Control Language Electronic engineering Hardware description languages Electronic design automation
53	HES-DVM™ HW/SW Validation Platform Hybrid Verification Platform HES-DVMTM is a Hybrid Verification and Validation Platform for Hardware and Software developers of SoC and ASIC designs up to 144M ASIC gates. Utilizing Add to Reading List Source URL: www.aldec.com Language: English - Date: 2015-02-02 17:14:32 Hardware verification languages Aldec Logic design Hardware emulation Hardware description languages Field-programmable gate array Joint Test Action Group Mentor Graphics Application-specific integrated circuit Electronic engineering Electronic design automation Digital electronics
54	EN164: Design of Computing Systems Lecture 04: Lab Foundations / Programmable logic Professor Sherief Reda http://scale.engin.brown.edu Electrical Sciences and Computer Engineering School of Engineering Add to Reading List Source URL: scale.engin.brown.edu Language: English - Date: 2014-03-23 13:26:52 Field-programmable gate array Gate array Programmable logic array Programmable logic device Altera Logic synthesis Array Electronic engineering Design Electronic design automation
55	Logic gates at the surface code threshold: Superconducting qubits poised for fault-tolerant quantum computing R. Barends,1, ∗ J. Kelly,1, ∗ A. Megrant,1 A. Veitia,2 D. Sank,1 E. Jeffrey,1 T. C. White,1 J. Mutus,1 A. Add to Reading List Source URL: www.ee.ucr.edu Language: English - Date: 2014-03-13 16:50:49 Physics Quantum error correction Qubit Controlled NOT gate Quantum computer Quantum gate Quantum circuit Charge qubit Phase qubit Quantum information science Theoretical computer science Quantum mechanics
56	Yosys - A Free Verilog Synthesis Suite Clifford Wolf, Johann Glaser† Johannes Kepler University, Austria Institute for Integrated Circuits , † Add to Reading List Source URL: www.clifford.at Language: English - Date: 2013-10-11 16:34:33 Electronic design Integrated circuits Verilog Field-programmable gate array Standard cell Application-specific integrated circuit Logic synthesis High-level synthesis VHDL Electronic engineering Electronic design automation Hardware description languages
57	Yosys Open SYnthesis Suite Clifford Wolf (http://www.clifford.at/yosys/) Clifford Wolf http://www.clifford.at/yosys/ Add to Reading List Source URL: www.clifford.at Language: English - Date: 2015-02-09 07:25:30 Hardware description languages Logic design Technical communication Verilog Register-transfer level VHDL Field-programmable gate array Application-specific integrated circuit Logic gate Electronic engineering Electronic design automation Digital electronics
58	Xilinx Training Course Listing Effective April 1, 2015 II Add to Reading List Source URL: japan.xilinx.com Language: English - Date: 2015-04-14 15:20:39 Reconfigurable computing Xilinx Field-programmable gate array MicroBlaze Logic synthesis Application-specific integrated circuit Soft microprocessor Embedded system Xilinx ISE Electronic engineering Electronics Digital electronics
59	OpenCores HDL modeling guidelines This document describes the OpenCores HDL modelling guidelines with some examples Brought to You By OpenCores Add to Reading List Source URL: cdn.opencores.org Language: English - Date: 2011-06-07 09:12:49 Electronic design Logic design OpenCores Wishbone Field-programmable gate array Verilog VHDL Semiconductor intellectual property core Application-specific integrated circuit Electronic engineering Electronics Hardware description languages
60	DO-254_BrochurePP1_Rev2012.02 Add to Reading List Source URL: www.aldec.com Language: English - Date: 2014-09-10 19:05:25 Electronic design Integrated circuits Fabless semiconductor companies Aldec Embedded systems Logic design Field-programmable gate array Integrated circuit design DO-254 Electronic engineering Electronics Digital electronics

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